The present invention relates to a nonvolatile memory device, in which a ferroelectric capacitor is connected in series to the gate electrode of a field effect transistor (FET).
A ferroelectric FET (FeFET) is a nonvolatile memory device including a ferroelectric and an FET in combination. An FeFET may have any of various types of device structures, which can be roughly classified into the categories of: MFS FeFETs; MFIS FeFETs and MFMIS FeFETs. As used herein, xe2x80x9cMFSxe2x80x9d, xe2x80x9cMFISxe2x80x9d and xe2x80x9cMFMISxe2x80x9d are the acronyms standing for metal-ferroelectric-semiconductor, metal-ferroelectric-insulator-semiconductor and metal-ferroelectric-metal-insulator-semiconductor, respectively.
FIG. 9 is a cross-sectional view illustrating a structure for an MFMIS FeFET for use in the present invention. As shown in FIG. 9, the MFMIS FeFET has a multilayer structure consisting of dielectric 34, floating gate electrode 35, ferroelectric 36 and control electrode 37 that have been stacked in this order on a p-type silicon (Si) substrate 31. In the p-type Si substrate 31, a pair of n-type heavily doped regions 32 and 33 has been defined as source and drain electrodes, respectively. In this structure, a ferroelectric capacitor has been formed on the floating gate electrode 35 of an FET, and the electrode 35 is used in common for the ferroelectric capacitor and FET. A structure, in which the electrode of a ferroelectric capacitor is connected to the gate electrode of an FET through a line, is also a type of MFMIS FeFET.
Next, it will be described how an MFMIS FeFET with such a structure operates as a nonvolatile memory device.
When a voltage Vg applied to the control electrode has its polarity inverted into a positive or negative value, the direction of polarization in the ferroelectric reverses. In the following description, to apply a positive voltage Vg to the control electrode will mean to write data xe2x80x9c1xe2x80x9d on the ferroelectric, while to apply a negative voltage Vg to the control electrode will mean to write data xe2x80x9c0xe2x80x9d on the ferroelectric.
Even after the voltage applied has been removed from the control electrode to allow the electrode to be floating, the polarization is left in the ferroelectric, which is called xe2x80x9cremanent polarizationxe2x80x9d. To read data out, a voltage is applied between the source/drain electrodes while allowing the control electrode to be floating. In this state, the potential level at the control electrode is believed to be close to the ground level, because there is a leakage current flowing due to the existence of resistive components and because there is also a coupling capacitance created between the electrode and a line connected thereto. On the other hand, the potential level at the floating gate electrode of the FET may be either positive or negative depending on the direction of remanent polarization existing in the ferroelectric capacitor. If the potential level at the floating gate electrode is positive and higher than the threshold voltage of the FET, then the FET turns ON, thus allowing a current to flow between the source and drain regions. Alternatively, if the potential level at the floating gate electrode is negative, then the FET turns OFF and no source-drain current flows. By comparing a sourcedrain current value Ids with a predetermined reference current value Iref and defining Ids greater than Iref and Ids less than Iref as representing data xe2x80x9c1xe2x80x9d and data xe2x80x9c0xe2x80x9d, respectively, the data written can be read out accurately.
By way of an illustrative example, a simulation will be run on the operation of an MFMIS FeFET that uses strontium bismuth tantalate (SrBi2Ta2O9) as its ferroelectric and silicon dioxide (SiO2) as its dielectric, respectively.
FIG. 10 illustrates an equivalent circuit for the FeFET.
Now it will be described with reference to FIG. 10 how the MFMIS FeFET operates. In FIG. 10, the ferroelectric capacitor, FET and control, source and drain electrodes are identified by the reference numerals 41, 42, 43, 44 and 45, respectively.
The parameters are set as follows. Suppose the SrBi2Ta2O9 has a thickness of 200 nm, a dielectric constant of 300 and a coercive voltage of 0.8 V, while the SiO2 has a thickness of 3.5 nm and a dielectric constant of 3.9. The f erroelectric capacitor, which is the MFM section of the MFMIS structure, has a polarization Pf and an interelectrode voltage Vf and is supplied with a voltage Vg at the control electrode thereof. As for the FET, or the MIS section of the MFMIS structure, a charge Qi has been stored in the gate, voltages Vd, Vi and Vs (where Vs=0 V) are applied to the drain, floating gate and source electrodes, respectively, and the potential level at the substrate is 0 V. And when the FET alone is operated by electrically disconnecting the ferroelectric capacitor from the FET, the threshold voltage vti of the FET is supposed to be 0.5 V.
A memory cell like this meets the following two Equations (1) and (2):
Pf(Vf)=Qi(Vi)xe2x80x83xe2x80x83(1)
Vg=Vf+Vixe2x80x83xe2x80x83(2)
combining these Equations (1) and (2) together, the following Equation (3)
Pf(Vf)=Qi(Vgxe2x88x92Vf)xe2x80x83xe2x80x83(3)
is derived.
FIG. 11A illustrates a Pfxe2x88x92Vf characteristic (which is a so-called xe2x80x9chysteresis loopxe2x80x9d) of the ferroelectric capacitor. In FIG. 11A, Pf values corresponding to increasing voltages are represented by the lower curve 1, while Pf values corresponding to decreasing voltages are represented by the upper curve 2. A voltage, at which Pf=0 C/cm2 in the Pfxe2x88x92Vf characteristic, is called a xe2x80x9ccoercive voltage Vcxe2x80x9d.
FIG. 11B illustrates a Qixe2x88x92Vi characteristic of the FET as a curve 51. This characteristic can be easily obtained by a well-known computation method for an MOS capacitor.
By performing a symmetry transformation on this Qixe2x88x92Vi characteristic about the Qi axis and shifting the resultant curve by Vg along the Vi axis, a Qixe2x88x92(Vgxe2x88x92Vf) characteristic can be obtained. Thereafter, the Pfxe2x88x92Vf and Qixe2x88x92(Vgxe2x88x92Vf) characteristics are plotted on the same graphic plane to obtain their intersection. As can be seen from Equation (3), this intersection represents the operating point of the FeFET. Supposing the voltage at the intersection is identified by Vx, Vf=Vx and Vi=Vgxe2x88x92Vx.
The operation of the FeFET will now be simulated by an operating point analysis technique using this graph.
First, it will be analyzed where the operating point is located when data xe2x80x9c1xe2x80x9d is written, i.e., a positive voltage Vg ( greater than 0 V) is applied to the control electrode. FIG. 12A illustrates a Pfxe2x88x92Vf characteristic 1 and 2 and a Qixe2x88x92(Vgxe2x88x92Vf) characteristic 52 where a voltage Vg of 15 V is applied to the control electrode. As shown in FIG. 12A, the voltage Vx at the intersection 53 is 3 V, and vf=3 V. Accordingly, Vi=12 V is obtained by Equation (2).
Next, it will be analyzed where the operating point is located when data xe2x80x9c0xe2x80x9d is written, i.e., a negative voltage vg ( less than 0 V) is applied to the control electrode. FIG. 12B illustrates a Pfxe2x88x92Vf characteristic 1 and 2 and a Qixe2x88x92(Vgxe2x88x92Vf) characteristic 54 where a voltage vg of xe2x88x9215 V is applied to the control electrode. As shown in FIG. 12B, the voltage Vx at the intersection 55 is xe2x88x923.5 V, and Vf =xe2x88x923.5 V. Accordingly, Vi=xe2x88x9211.5 V is obtained by Equation (2).
If data is saved in such a state, the control electrode is floating. However, there is a voltage drop due to a leakage current flowing through the ferroelectric and FET and there is also a coupling capacitance between the electrodes. For that reason, the control electrode voltage Vg is believed to be almost 0 V. Thus, the following discussion will be based on the supposition that Vg=0 V (Vi=Vgxe2x88x92Vx≈xe2x88x92Vx) while the control electrode is floating.
FIG. 13 illustrates a Pfxe2x88x92Vf characteristic 1 and 2 and a Qixe2x88x92(Vgxe2x88x92Vf) characteristic 56, which represent the operation state of the device on which data is retained. The operating point is determined by the hysteresis characteristic to be exhibited by the ferroelectric after the binary data has been written. Specifically, while data xe2x80x9c1xe2x80x9d is retained, Vf decreases from 3 V, which was applied to the ferroelectric when the data xe2x80x9c1xe2x80x9d was written. Accordingly, the intersection between the upper voltage-fall curve 2 of the hysteresis loop and the characteristic 56 will be the operating point 3 of the data xe2x80x9c1xe2x80x9d retaining operation. On the other hand, while data xe2x80x9c0xe2x80x9d is retained, Vf increases from xe2x88x923.5 V, which was applied to the ferroelectric when the data xe2x80x9c0xe2x80x9d was written. Accordingly, the intersection between the lower voltage-rise curve 1 of the hysteresis loop and the characteristic 56 will be the operating point 4 of the data xe2x80x9c0xe2x80x9d retaining operation.
As shown in FIG. 13, the operating point Vx of the data xe2x80x9c1xe2x80x9d retaining operation is xe2x88x920.8 V, and Vf=xe2x88x920.8 V. Since Vg=0 V during this retention operation, Vi=0.8 V. On the other hand, the operating point Vx of the data xe2x80x9c0xe2x80x9d retaining operation is 0.7 V, and Vf=0.7 V. Since Vg=0 V during this retention operation, Vi=xe2x88x920.7 V. That is to say, since Vi greater than Vti while the data xe2x80x9c1xe2x80x9d is being retained, the FET is ON. Conversely, since Vi  less than Vti while the data xe2x80x9c0xe2x80x9d is being retained, the FET is OFF.
Finally, data is read out by applying a voltage Vd of 0.5 V to the drain electrode while the control electrode is still floating. If the voltage at the floating electrode is larger than the threshold voltage of the FET (i.e., when Vi greater than Vti), then the FET turns ON and a drain current flows. Alternatively, if the voltage at the floating electrode is smaller than the threshold voltage of the FET (i.e., when Vi less than ti), then the FET turns OFF and no drain current flows.
In this example, the voltage Vi of 0.8 V obtained by analyzing the operating point of the data xe2x80x9c1xe2x80x9d retaining operation is larger than the threshold voltage Vti of 0.5 V. Thus, the FeFET can read the data xe2x80x9c1xe2x80x9d out. On the other hand, the voltage Vi of xe2x88x920.7 V obtained by analyzing the operating point of the data xe2x80x9c0xe2x80x9d retaining operation is smaller than the threshold voltage Vti of 0.5 V. Thus, the FeFET can also read the data xe2x80x9c0xe2x80x9d out.
T. Nakamura et al., xe2x80x9cElectrical Characteristics of MFMIS FET Using STN Filmsxe2x80x9d, Technical Report of IEICE, ED98-255, SDM98-208, pp. 63-69, Feb. 1999 showed an example in which Vg was set to 0 V for a read operation. In the foregoing operation simulation, Vg is also supposed to be almost 0 V. Accordingly, similar results are obtained in either case.
However, a ferroelectric-based nonvolatile memory device has a so-called xe2x80x9cimprint degradationxe2x80x9d problem. Specifically, if data is retained there for a long time, the device will no longer be able to read the data out accurately, because the polarization will have decreased at that time so that the device will have its operating point changed. In the foregoing example, the voltage Vi, representing the operating point of the data xe2x80x9c1xe2x80x9d retaining operation, is 0.8 V. In this case, however, a margin available to the FeFET that should meet the turn-ON condition (i.e., Vi  greater than Vti), or a maximum allowable variation of the floating gate electrode voltage Vi within which the data xe2x80x9c1xe2x80x9d can be written or read out accurately, is as small as 0.3 V. Accordingly, if Vi decreases by more than 0.3 V due to the decrease in polarization, then the FET cannot satisfy the turn-ON condition anymore. As a result, the data xe2x80x9c1xe2x80x9d can no longer be read out accurately. As for the data xe2x80x9c0xe2x80x9d retaining operation on the other hand, Vi=xe2x88x920.7 V and there is a sufficient margin of 1.2 V available to the FET that should meet the turn-OFF condition (i.e., Vi less than Vti).
While data xe2x80x9c1xe2x80x9d is retained, the FET is ON as described above. Accordingly, in an array of memory cells in which the respective drain electrodes of multiple FeFETs are connected to a bit line, a select transistor should be additionally provided for each of those drain electrodes. See Japanese Laid-Open Publication Nos. 5-205487 and 5-206411 (both published on Aug. 13, 1999). Therefore, when a semiconductor memory device, including multiple FeFETs arranged in matrix, performs reading by detecting the level of a drain current flowing through particular one of the FeFETs, the drain currents of the other FeFETs in the retention state should be blocked using select transistors. For that reason, it is difficult to increase the number of FeFETs integrated as intended.
It is therefore an object of the present invention to provide a method of setting a best voltage for a semiconductor memory device to read out data while improving the retention characteristic of the device.
An inventive data reading method is applicable to a semiconductor memory device that includes: a capacitor having two electrodes and a ferroelectric interposed between the electrodes; and a field effect transistor having source, drain and gate electrodes. In the device, one of the two electrodes of the capacitor is connected to, or used in common as, the gate electrode of the transistor, while the other electrode of the capacitor is used as a control electrode. In this reading method, a voltage is applied to the control electrode, thereby changing a polarization of the ferroelectric and eventually a channel resistance of the transistor so that the channel resistance can represent binary data depending on whether the resistance is high or low. This reading method is characterized by applying a positive voltage to the control electrode if a threshold voltage of the transistor is positive, and by applying a negative voltage to the control electrode if the threshold voltage of the transistor is negative. According to this data reading method, a particular voltage Vread is applied to the control electrode during a read operation, thereby substantially eliminating the difference between the turn-OFF margin of 1.2 V and the turn-ON margin of 0.3 V. That is to say, since the margin allowed for the turn-ON condition Vi greater than Vti can be increased, the retention characteristic of the device improves greatly.
In one embodiment of the present invention, if the threshold voltage of the transistor is positive, the polarization of the capacitor is changed by increasing an interelectrode voltage from 0 V on the supposition that a remanent polarization of 0 C/cm2 initially exists in the capacitor. Then, the voltage applied to the control electrode is set to a value deviated by no greater than xc2x120% from a sum of a first interelectrode voltage value and the positive threshold voltage of the transistor. The first interelectrode voltage value is associated with a first polarization value corresponding to a first quantity of charge created in a channel of the transistor when the positive threshold voltage is applied to the gate electrode of the transistor. On the other hand, if the threshold voltage of the transistor is negative, the polarization of the capacitor is changed by decreasing the interelectrode voltage from 0 V on the supposition that the remanent polarization of 0 C/cm2 initially exists in the capacitor. Then, the voltage applied to the control electrode is set to a value deviated by no greater than xc2x120% from a sum of a second interelectrode voltage value and the negative threshold voltage of the transistor. The second interelectrode voltage value is associated with a second polarization value corresponding to a second quantity of charge created in the channel of the transistor when the negative threshold voltage is applied to the gate electrode of the transistor.
In this embodiment, by increasing the interelectrode voltage Vf from 0 V with a polarization of 0 C/cm2 supposed to initially exist in a ferroelectric capacitor of an MFMIS FeFET, the operating point, or a read voltage, is set by reference to the Pfxe2x88x92vf characteristic of the capacitor and the Qixe2x88x92vi characteristic of the FET. That is to say, the read voltage is set on the supposition that Pf=0 C/cm2, which is a worst-case scenario possibly caused by a decrease in polarization after data has been retained for a long time. Accordingly, even if the polarization decreases during the data xe2x80x9c1xe2x80x9d retaining operation, the FET never fails to turn ON until the Pf value actually reaches 0 C/cm2, and data can be read out accurately. In this embodiment, the read voltage applied to the control electrode should fall within a range of xc2x120% in view of variations of the threshold voltage and polarization. This is because the threshold voltage of an FET is variable by xc2x115% due to a variation in the thickness of a film deposited, the mask overlay accuracy, the depth of an etched part, the ion implant dose and/or the degree of damage, and because the polarization of a ferroelectric is also variable by xc2x15%.
An inventive data writing method is applicable to a semiconductor memory device that includes: a capacitor having two electrodes and a ferroelectric interposed between the electrodes; and a field effect transistor having source, drain and gate electrodes. In the device, one of the two electrodes of the capacitor is connected to, or used in common as, the gate electrode of the transistor, while the other electrode of the capacitor is used as a control electrode. In this writing method, a voltage is applied to the control electrode, thereby changing a polarization of the ferroelectric and eventually changing a channel resistance of the transistor so that the channel resistance can represent binary data depending on whether the resistance is high or low. This writing method is characterized in that the voltage applied to the control electrode falls within such a range as to turn OFF the transistor after the voltage applied to the electrode has been removed therefrom. According to this data writing method, no matter whether data xe2x80x9c0xe2x80x9d or xe2x80x9c0xe2x80x9d is retained, the FET is always OFF and no drain current flows.
An inventive method for driving a semiconductor memory device includes the steps of: writing data on the device by the inventive writing method; and then applying a reset voltage to the control electrode. According to this driving method, after a write operation has been performed, the interelectrode voltage quickly reaches the operating point of the retaining operation.
In reading out data from a semiconductor memory device, on which data has been written by the inventive writing method, if a threshold voltage of the transistor is positive, then a positive voltage, which is equal to or smaller than the threshold voltage of the transistor, is applied to the control electrode. Alternatively, if the threshold voltage of the transistor is negative, then a negative voltage, which is equal to or larger than the threshold voltage of the transistor, is applied to the control electrode. According to this data reading method, even an FeFET, which is OFF while data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is retained therein, turns ON in reading out the data xe2x80x9c1xe2x80x9d and turns OFF in reading out the data xe2x80x9c0xe2x80x9d. As a result, the data can be read out accurately.
The inventive data reading method is also applicable to a memory array in which multiple semiconductor memory devices are arranged in matrix. In this array, each of those memory devices includes: the capacitor having the two electrodes and the ferroelectric; the field effect transistor having the source, drain and gate electrodes; and a gate selecting transistor also having source, drain and gate electrodes. In the memory device, the drain and source electrodes of the field effect transistor are connected to a bit line and a source line, respectively. The control electrode of the memory device is connected to the source electrode of the gate selecting transistor. And the gate and drain electrodes of the gate selecting transistor are connected to first and second word lines, respectively. In such an embodiment, data still can be read out accurately even when no select transistor exists between the drain electrode and bit line (or between the source electrode and source line). Accordingly, a much greater number of devices can be integrated on a single chip.
As can be seen, according to the present invention, an increased voltage margin is available when the FeFET should perform a read operation. In addition, even if the polarization value of the ferroelectric capacitor changes, the read operation can be performed correctly until the 15 polarization reaches 0 C/cm2, which is the worst-case scenario. Furthermore, no select transistor is needed between the drain electrode and bit line.